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Add LDIV, STIV instructions

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This commit is contained in:
Joscha 2019-11-06 14:17:32 +00:00
parent 9532d0487b
commit 04036bb047
2 changed files with 22 additions and 12 deletions
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6
src/Mima/Instruction.hs
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@ -14,14 +14,14 @@ import Data.Word
import Mima.Util
import Mima.Word
data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN
data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN | STIV | LDIV
deriving (Show, Eq, Ord)
instance ToText SmallOpcode where
toText = T.pack . show
allSmallOpcodes :: [SmallOpcode]
allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN]
allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN, STIV, LDIV]
getSmallOpcode :: SmallOpcode -> Word32
getSmallOpcode LDC = 0
@ -34,6 +34,8 @@ getSmallOpcode XOR = 6
getSmallOpcode EQL = 7
getSmallOpcode JMP = 8
getSmallOpcode JMN = 9
getSmallOpcode STIV = 10
getSmallOpcode LDIV = 11
smallOpcodeMap :: Map.Map Word32 SmallOpcode
smallOpcodeMap = Map.fromList [(getSmallOpcode oc, oc) | oc <- allSmallOpcodes]

8
src/Mima/State.hs
View file

@ -91,6 +91,14 @@ executeSmallOpcode XOR addr ms = incrementIp ms{msAcc = msAcc ms `xor` readAt ad
executeSmallOpcode EQL addr ms = incrementIp ms{msAcc = boolToWord $ msAcc ms == readAt addr (msMemory ms)}
executeSmallOpcode JMP addr ms = pure ms{msIp = addr}
executeSmallOpcode JMN addr ms = if topBit (msAcc ms) then pure ms{msIp = addr} else incrementIp ms
executeSmallOpcode STIV addr ms =
let mem = msMemory ms
indirAddr = address $ readAt addr mem
in incrementIp ms{msMemory = writeAt indirAddr (msAcc ms) mem}
executeSmallOpcode LDIV addr ms =
let mem = msMemory ms
indirAddr = address $ readAt addr mem
in incrementIp ms{msAcc = readAt indirAddr mem}
executeLargeOpcode :: LargeOpcode -> MimaState -> Either ExecException MimaState
executeLargeOpcode HALT ms =