Swap STIV and LDIV
Now the opcodes match the ones at https://github.com/mkiesinger/mimaFPGA#op-codes
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1 changed files with 4 additions and 4 deletions
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@ -14,14 +14,14 @@ import Data.Word
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import Mima.Util
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import Mima.Util
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import Mima.Word
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import Mima.Word
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data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN | STIV | LDIV
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data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN | LDIV | STIV
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deriving (Show, Eq, Ord)
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deriving (Show, Eq, Ord)
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instance ToText SmallOpcode where
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instance ToText SmallOpcode where
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toText = T.pack . show
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toText = T.pack . show
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allSmallOpcodes :: [SmallOpcode]
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allSmallOpcodes :: [SmallOpcode]
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allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN, STIV, LDIV]
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allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN, LDIV, STIV]
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getSmallOpcode :: SmallOpcode -> Word32
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getSmallOpcode :: SmallOpcode -> Word32
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getSmallOpcode LDC = 0
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getSmallOpcode LDC = 0
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@ -34,8 +34,8 @@ getSmallOpcode XOR = 6
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getSmallOpcode EQL = 7
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getSmallOpcode EQL = 7
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getSmallOpcode JMP = 8
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getSmallOpcode JMP = 8
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getSmallOpcode JMN = 9
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getSmallOpcode JMN = 9
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getSmallOpcode STIV = 10
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getSmallOpcode LDIV = 10
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getSmallOpcode LDIV = 11
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getSmallOpcode STIV = 11
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smallOpcodeMap :: Map.Map Word32 SmallOpcode
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smallOpcodeMap :: Map.Map Word32 SmallOpcode
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smallOpcodeMap = Map.fromList [(getSmallOpcode oc, oc) | oc <- allSmallOpcodes]
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smallOpcodeMap = Map.fromList [(getSmallOpcode oc, oc) | oc <- allSmallOpcodes]
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