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Swap STIV and LDIV

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Now the opcodes match the ones at
https://github.com/mkiesinger/mimaFPGA#op-codes
This commit is contained in:
Joscha 2019-11-06 20:56:08 +00:00
parent d9d8f4e0b9
commit 0c780cfece
1 changed files with 4 additions and 4 deletions
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8
src/Mima/Instruction.hs
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@ -14,14 +14,14 @@ import Data.Word
import Mima.Util
import Mima.Word
data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN | STIV | LDIV
data SmallOpcode = LDC | LDV | STV | ADD | AND | OR | XOR | EQL | JMP | JMN | LDIV | STIV
deriving (Show, Eq, Ord)
instance ToText SmallOpcode where
toText = T.pack . show
allSmallOpcodes :: [SmallOpcode]
allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN, STIV, LDIV]
allSmallOpcodes = [LDC, LDV, STV, ADD, AND, OR, XOR, EQL, JMP, JMN, LDIV, STIV]
getSmallOpcode :: SmallOpcode -> Word32
getSmallOpcode LDC = 0
@ -34,8 +34,8 @@ getSmallOpcode XOR = 6
getSmallOpcode EQL = 7
getSmallOpcode JMP = 8
getSmallOpcode JMN = 9
getSmallOpcode STIV = 10
getSmallOpcode LDIV = 11
getSmallOpcode LDIV = 10
getSmallOpcode STIV = 11
smallOpcodeMap :: Map.Map Word32 SmallOpcode
smallOpcodeMap = Map.fromList [(getSmallOpcode oc, oc) | oc <- allSmallOpcodes]