From 6ac5bfc9e715fe742baa101ae0d0efdb5d556c85 Mon Sep 17 00:00:00 2001 From: Joscha Date: Sun, 10 Nov 2019 11:37:55 +0000 Subject: [PATCH] Add example for nested CALLs with stack --- examples/call_ret_stack.mima | Bin 0 -> 927 bytes examples/call_ret_stack.mimasm | 71 +++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 examples/call_ret_stack.mima create mode 100644 examples/call_ret_stack.mimasm diff --git a/examples/call_ret_stack.mima b/examples/call_ret_stack.mima new file mode 100644 index 0000000000000000000000000000000000000000..e50c406bce42ce48c47638ab96dfa09d5a7f4648 GIT binary patch literal 927 zcmZQzNMQg2{{R2M^e91W2naAR{9<5KU|=}Fa01L`Qea^CK&$VEFa_|91w41B^Ns7#P1oL>L&qGcbTvawsq`d>&aLgzzmm1Oy-<005)c85IBk literal 0 HcmV?d00001 diff --git a/examples/call_ret_stack.mimasm b/examples/call_ret_stack.mimasm new file mode 100644 index 0000000..0a4800f --- /dev/null +++ b/examples/call_ret_stack.mimasm @@ -0,0 +1,71 @@ +IAR = main +ACC = 0 +RA = 0 +SP = 0xfffff + +; In this example, the stack pointer points to the next free address +; below the stack. The stack grows downwards from large to small +; addresses. The stack has no stack frames to simplify the program. + +counter: LIT 0 + +100: +main: + ; set counter bit 0 + LDV counter + ADC 0x01 + STV counter + + ; Since we're top-level, we don't need to (re-)store our RA when calling + CALL sub-a + + ; set counter bit 1 + LDV counter + ADC 0x02 + STV counter + + HALT + +200: +sub-a: + ; Set counter bit 2 + LDV counter + ADC 0x04 + STV counter + + ;; Store the current RA on the stack + ; Store the RA at current position of stack pointer + LDRA + STVR 0 + ; Move stack pointer by 1 since the stack grew + LDSP + ADC -1 + STSP + + ; Call the subfunction + CALL sub-b + + ;; Pop and restore the RA from the stack + ; Read RA from the top of the stack + LDVR 1 + STRA + ; Remove top element from stack + LDSP + ADC 1 + STSP + + ; Set counter bit 3 + LDV counter + ADC 0x08 + STV counter + + RET + +300: +sub-b: + ; Set counter bit 4 + LDV counter + ADC 0x10 + STV counter + + RET