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Make README more readable

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Joscha 2019-11-07 09:59:07 +00:00
parent 3eb9430208
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@ -62,37 +62,39 @@ ignored. They don't have to be set to 0.
### Opcodes ### Opcodes
| Opcode | Name | Function | Notes | | Opcode | Name | Function |
|--------|---------------------------------------------|--------------------------------|----------------------------------| |--------|---------------------------------------------|--------------------------------|
| `0` | `LDC c` (load constant) | `c -> ACC` | Bits 23-20 of `ACC` are set to 0 | | `0` | `LDC c` (load constant) | `c -> ACC` |
| `1` | `LDV a` (load value) | `<a> -> ACC` | | | `1` | `LDV a` (load value) | `<a> -> ACC` |
| `2` | `STV a` (store value) | `ACC -> <a>` | | | `2` | `STV a` (store value) | `ACC -> <a>` |
| `3` | `ADD a` | `ACC + <a> -> ACC` | | | `3` | `ADD a` | `ACC + <a> -> ACC` |
| `4` | `AND a` | `ACC and <a> -> ACC` | Bitwise operation | | `4` | `AND a` | `ACC and <a> -> ACC` |
| `5` | `OR a` | `ACC or <a> -> ACC` | Bitwise operation | | `5` | `OR a` | `ACC or <a> -> ACC` |
| `6` | `XOR a` | `ACC xor <a> -> ACC` | Bitwise operation | | `6` | `XOR a` | `ACC xor <a> -> ACC` |
| `7` | `EQL a` (equal) | `(ACC == <a> ? -1 : 0) -> ACC` | | | `7` | `EQL a` (equal) | `(ACC == <a> ? -1 : 0) -> ACC` |
| `8` | `JMP a` (jump) | `a -> IAR` | | | `8` | `JMP a` (jump) | `a -> IAR` |
| `9` | `JMN a` (jump if negative) | `if (ACC < 0) {a -> IAR}` | | | `9` | `JMN a` (jump if negative) | `if (ACC < 0) {a -> IAR}` |
| `A` | `LDIV a` (load indirect value) | `<<a>> -> ACC` | | | `A` | `LDIV a` (load indirect value) | `<<a>> -> ACC` |
| `B` | `STIV a` (store indirect value) | `ACC -> <<a>>` | | | `B` | `STIV a` (store indirect value) | `ACC -> <<a>>` |
| `C` | `CALL a` | `IAR -> RA; JMP a` | | | `C` | `CALL a` | `IAR -> RA; JMP a` |
| `D` | `LDVR d` (load value with relative offset) | `<SP + d> -> ACC` | | | `D` | `LDVR d` (load value with relative offset) | `<SP + d> -> ACC` |
| `E` | `STVR d` (store value with relative offset) | `ACC -> <SP + d>` | | | `E` | `STVR d` (store value with relative offset) | `ACC -> <SP + d>` |
| `F0` | `HALT` | Halt execution | | | `F0` | `HALT` | Halt execution |
| `F1` | `NOT` | `not ACC -> ACC` | Bitwise operation | | `F1` | `NOT` | `not ACC -> ACC` |
| `F2` | `RAR` (rotate ACC right) | `ACC >> 1 -> ACC` | See below | | `F2` | `RAR` (rotate ACC right) | `ACC >> 1 -> ACC` |
| `F3` | `RET` (return) | `RA -> IAR` | | | `F3` | `RET` (return) | `RA -> IAR` |
| `F4` | `LDSP` (load from SP) | `SP -> ACC` | | | `F4` | `LDRA` (load from RA) | `RA -> ACC` |
| `F5` | `STSP` (store to SP) | `ACC -> SP` | | | `F5` | `STRA` (store to RA) | `ACC -> RA` |
| `F6` | `LDFP` (load from FP) | `FP -> ACC` | | | `F6` | `LDSP` (load from SP) | `SP -> ACC` |
| `F7` | `STFP` (store to FP) | `ACC -> FP` | | | `F7` | `STSP` (store to SP) | `ACC -> SP` |
| `F8` | `LDRA` (load from RA) | `RA -> ACC` | | | `F8` | `LDFP` (load from FP) | `FP -> ACC` |
| `F9` | `STRA` (store to RA) | `ACC -> RA` | | | `F9` | `STFP` (store to FP) | `ACC -> FP` |
| `FA` | `ADC c` (add constant) | `ACC + c -> ACC` | See below | | `FA` | `ADC c` (add constant) | `ACC + c -> ACC` |
- `RAR` shifts all bits in the `ACC` right by one. The rightmost bit wraps around to the leftmost position. * `LDC c` sets bits 23-20 of `ACC` to 0.
- `ADC c` interprets bits 15-0 as a signed integer, whose value is then added to the `ACC`'s current value. * `ADD a`, `AND a`, `OR a`, `XOR a` and `NOT` are bitwise operations
* `RAR` shifts all bits in the `ACC` right by one. The rightmost bit wraps around to the leftmost position.
* `ADC c` interprets bits 15-0 as a signed integer, whose value is then added to the `ACC`'s current value.
## File format ## File format
@ -118,7 +120,7 @@ The registers and memory are stored as follows:
| Word | Content | | Word | Content |
|--------------:|-------------| |--------------:|-------------|
| 0 | `IR` | | 0 | `IAR` |
| 1 | `ACC` | | 1 | `ACC` |
| 2 | `RA` | | 2 | `RA` |
| 3 | `SP` | | 3 | `SP` |