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Clear up some ambiguities

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Joscha 2019-11-06 22:44:35 +00:00
parent 665413f420
commit 6f6f32b5cf
1 changed files with 41 additions and 38 deletions
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README.md
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@ -4,23 +4,26 @@
### General
In the following sections, `<a>` means "the value at the address
`a`". In the case of `<<a>>`, bits 19-0 of `<a>` are interpreted as
the address.
The MiMa uses words of 24 bits and addresses of 20 bits.
Each step, the MiMa fetches the value at the address stored in the
`IAR`, interprets it as an instruction and executes it. If the
instruction does not explicitly modify the `IAR`, it is incremented by
1 automatically.
instruction does not explicitly modify the `IAR`, the `IAR` it is
incremented by one automatically.
During execution, multiple situations can be encountered where
execution should not be continued, for example:
During execution, the following situations can be encountered where
execution should not be continued:
* After the `HALT` instruction was executed
* The value stored at the current address of the `IAR` cannot be
decoded to a valid instruction
* The instruction pointer is at value `0xFFFFF` and the instruction
does not modify the `IAR`
* The `HALT` instruction was executed
* The value at `<IAR>` cannot be decoded to a valid instruction
* The `IAR` is `0xFFFFF` and an instruction was executed that did not
modify the `IAR`
In those cases, a MiMa emulator should stop execution and show a
In these cases, a MiMa emulator should stop execution and show a
suitable error message explaining why execution could not continue.
### Instructions
@ -57,8 +60,8 @@ if at all, a 16-bit value as argument.
### Opcodes
| Opcode | Name | Function | Notes |
|--------|---------------------------------------------|--------------------------------|------------------------------------|
| `0` | `LDC c` (load constant) | `c -> ACC` | Upper 4 bits of `ACC` are set to 0 |
|--------|---------------------------------------------|--------------------------------|----------------------------------|
| `0` | `LDC c` (load constant) | `c -> ACC` | Bits 23-20 of `ACC` are set to 0 |
| `1` | `LDV a` (load value) | `<a> -> ACC` | |
| `2` | `STV a` (store value) | `ACC -> <a>` | |
| `3` | `ADD a` | `ACC + <a> -> ACC` | |
@ -68,8 +71,8 @@ if at all, a 16-bit value as argument.
| `7` | `EQL a` (equal) | `(ACC == <a> ? -1 : 0) -> ACC` | |
| `8` | `JMP a` (jump) | `a -> IAR` | |
| `9` | `JMN a` (jump if negative) | `if (ACC < 0) {a -> IAR}` | |
| `A` | `LDIV a` (load indirect value) | `<<a>> -> ACC` | Upper 4 bits of `<a>` are ignored |
| `B` | `STIV a` (store indirect value) | `ACC -> <<a>>` | Upper 4 bits of `<a>` are ignored |
| `A` | `LDIV a` (load indirect value) | `<<a>> -> ACC` | |
| `B` | `STIV a` (store indirect value) | `ACC -> <<a>>` | |
| `C` | `CALL a` | `IAR -> RA; JMP a` | |
| `D` | `LDVR d` (load value with relative offset) | `<SP + d> -> ACC` | |
| `E` | `STVR d` (store value with relative offset) | `ACC -> <SP + d>` | |